1. Technical Field
The present invention generally relates to a semiconductor device and methods for manufacturing the semiconductor device and, more particularly, to a field effect transistor having elevated source and drain regions and methods for manufacturing the same.
2. Description of the Related Art
As more highly integrated semiconductor integrated circuit devices are developed, attention must be given to overcoming performance and manufacturing problems which arise when the elements of the circuit devices are reduced in size and positioned closely together. In the case of field effect transistors (FETs), such problems include parasitic capacitance, junction leakage, and short-channel effects. For example, low resistance contacts to the source/drain regions of a transistor are often provided by forming silicide layers such as titanium silicide (TiSi.sub.2) or cobalt silicide (CoSi.sub.2) on the source and drain regions thereof by a silicide or salicide (self-aligned silicide) process. These silicide and salicide processes can damage the source/drain regions and cause junction leakage. In addition, the source and drain regions of FETs are generally formed by implanting impurities into the semiconductor substrate on which the transistor is formed. In FETs having short-channels (e.g., less than about 3 microns), implanting these impurities too deeply into the substrate can cause short-channel effects to become significant.
FETs having elevated source and drain regions have been developed to address these problems. FIG. 1 is a cross-sectional view of a conventional FET 10 having elevated source and drain regions. FET 10 is formed in an active area 13 of a semiconductor substrate 15 which is defined by a shallow trench isolation structure 17. Source diffusion region 19 and drain diffusion region 21 are formed in the active area 13 with a channel region 23 therebetween. A gate structure 25 is spaced from channel region 23 by a gate insulating film 27. A sidewall insulator 29 is formed on the sidewalls of gate structure 25. Elevated source region 31 and elevated drain region 33 of epitaxial silicon are formed on source diffusion region 19 and drain diffusion region 21, respectively. Since silicide layers for reducing contact resistance are formed on the elevated source and drain regions, source and drain diffusion regions 19 and 21 are not damaged and the junction leakage resulting from such damage can be avoided. In addition, since impurities for forming the source and drain diffusion regions are implanted through the elevated source and drain regions, shallow source and drain diffusion regions may be formed in semiconductor substrate 15, thereby reducing the impact of short-channel effects.
Elevated source and drain regions such as those shown in FIG. 1 are generally formed by selective epitaxial growth. Such selective epitaxial growth causes the elevated source and drain regions to have facets which are designated in FIG. 1 by reference numbers 35 and 37. When impurities are implanted in semiconductor substrate 15 through elevated source and drain regions having facets, the impurities which pass through the relatively thin portions of the raised regions defined by the facets penetrate more deeply into the portions of semiconductor substrate 15 designated by reference numeral 38 in FIG. 1 than the impurities which pass through the thicker portions of the elevated regions. These deeply implanted impurities can increase the significance of short-channel effects. In addition, silicide processes can create spikes at the location of these facets, and the spikes may penetrate into the underlying semiconductor substrate and through the underlying junctions, thereby shorting the source/drain to the substrate.
To overcome the problems associated with facets, a solid phase epitaxial growth process may be used. In this process, an amorphous silicon layer is deposited and then annealed. As a result of the annealing, one portion of the amorphous silicon layer is converted to an epitaxial layer and another portion of the amorphous silicon layer is converted to a polysilicon layer. However, since the etching selectivity between epitaxial silicon and polysilicon generated by this growth process is very low, it is difficult to completely remove the polysilicon layer to leave the epitaxial layer as the elevated source and drain regions.
Accordingly, it would be desirable to provide a FET and methods for manufacturing the same which overcome these and other problems.